This invention relates to the electronic design of integrated circuit chips and packages and more particularly, to a static timing analysis which is required to ensure the functionality and performance of the integrated circuit.
Conventional static timing analysis normally assumes static loads on nets. Coupling (e.g., interactions between adjacent wires) causes interactions which are not easily handled in conventional static timing analysis. One reason for the problems is that coupling can prevent the levelization of the logic network on which static timing analysis algorithms depend.
A vital part of the design of a digital system is the verification of the performance of the system. One method for verifying performance is to simulate the system in a simulator capable of modeling the behavior and delays of the system components. However, the number of possible data patterns which can be processed by the system is so large (exponential in the number of system inputs and state storage elements) even for very small systems, that only an extremely small fraction of these patterns can ever be simulated. Thus, a complete performance verification cannot be accomplished through simulation alone.
An alternative method for performance verification is a static timing analysis. This method is typically applied to synchronous circuits, in which a clock is used to control latches which store the results of logical operations performed in combinational logic networks, thus synchronizing the operation of the system. Proper operation of such systems requires that the correct data be present at a latch input before the clock event which stores the data into the latch, and also that the correct data be held at the latch input until it has been stored into the latch.
Static timing analysis verifies these conditions by determining the longest and/or the shortest paths through the network, or equivalently, by determining the latest possible time that correct data may arrive (become stable) at any given point of the system (e.g., a latch input) and/or the earliest that the correct data may be removed (become unstable) at any given point of the system. This is done without regard to the particular data values propagating through the system, and is thus able to completely verify the system performance without having to explore the enormous volume of possible data patterns.
Static timing analyzers typically deal with arrival times (ATs) and required arrival times (RATs). These times are generally specified with respect to the beginning of a cycle whose period is determined by a clock used to synchronize the system. Such analyzers typically operate on a timing graph containing nodes at which ATs and RATs are computed and directed edges which interconnect the nodes and which represent the time (delay) it takes for a value change on the source node to propagate to the sink node. The timing graph for a synchronous system will be acyclic (ignoring possible edges through latches). In systems having multiple clocks, these ATs and RATs are typically specified relative to different time frames and translations must be performed between these different time frames. One method for performing this translation is described in U.S. Pat. No. 5,210,700 to Tom.
The late mode AT of a node represents the latest time that the node value may become stable, while the late mode RAT represents the earliest time at which the node value needs to become stable to ensure that the node does not contribute to an improper system operation. Similarly, the early mode AT of a node represents the earliest time at which the node value may become unstable, and the early mode RAT represents the latest that the node value needs to held stable to ensure that the node does not contribute to improper system operation.
Static timing analyzers typically operate in one of two ways: a path oriented mode or a block oriented mode.
Path oriented analyzers trace the various latch-to-latch or input-to-output paths in the system. A separate AT is computed for a given node along each path leading to the node. Because the number of paths through a system can be very large (exponential in the number of elements in a path), this method takes a long time to fully analyze a system. Explicit or implicit methods can be used to prune the paths to be traced, but such pruning cannot completely solve the run time problem. One example of a path tracing static timing analysis method is described in U.S. Pat. No. 5,648,909 to Biro, et al.
Block oriented analyzers perform a levelization, or topological sort of the network (which is possible because the timing graph is acyclic) and then compute ATs in this sort order. In this way, the ATs of all predecessors of a node (nodes from which a path exists to the node) are computed before the AT of the node. Only a single AT needs to be computed for each node in the network. In the late (early) mode, it is the max (min) over all in-edges to the node of the AT of the edge source plus the edge delay. RATs are computed in reverse order on this topologically sorted network. The topological sort can be done explicitly or implicitly as a result of a depth first search, as described in U.S. Pat. No. 5,508,937 to Abato, et al.
It is also possible to update incrementally the results of a static timing analysis when some timing-relevant characteristics of the system under analysis change. Such changes can be modeled as additions, deletions, or changes to the delay value of edges in the delay graph. A method for performing such incremental timing updates is described in the previously mentioned U.S. Pat. No. 5,508,937.
More general information on static timing analysis can be found in an article by R. B. Hitchcock, Sr., entitled xe2x80x9cTiming Verification and the Timing Analysis Programxe2x80x9d, published in the Proceedings of the 18th Design Automation Conference, 1982, pp. 594-604, and in U.S. Pat. No. 4,263,651 to Donath et al.
The delays of edges in a timing graph typically reflect the delay through either a block (circuit) in the system, or from the source to a sink of a net in the system. In a system implemented with CMOS integrated circuits both of these delays will typically depend on the capacitive load on the net being driven by a block or whose delay is being computed, and on the signal slew (defined as the transition time or rise or fall time) at the source node of the edge. Traditionally, the capacitive load has been assumed to be a capacitance coupled to ground. In modern integrated circuits, the wires comprising the nets of the integrated circuit are physically very close together, and thus the coupling capacitance between them is often greater than the capacitance from the net to ground. Since these neighboring wires will be switching, the grounded capacitance assumption is invalid.
Accordingly, it is an object of the invention to factor in coupling effects in a static timing analysis to be performed on an integrated circuit chip or module being designed.
It is another object of the invention to model wire interactions as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied.
It is still another object to model the cyclic relationships caused by wire coupling and to safely bound the system timing in a limited number of iterations.
It is yet another object to determine the periods during which the effective load of a given net (i.e., a victim) is affected by transitions on a neighboring net (i.e., an aggressor).
It is a further object to compute the worst case effective load on a victim net based on the arrival times and slews on the victim and aggressor nets.
It is still a further object to replace the capacitance Cc between a victim net and an aggressor net with (1+K)Cc for a late mode and (1xe2x88x92K)Cc for an early mode.
It is still another object to use the ratio between victim and aggressor transitions to determine statically the effective loading seen by the victim.
It is yet another object to interactively time the design until the values for K of all the nets converge or until a user predetermined maximum is reached.
It is a more particular object to use the degree of overlap between the victim and aggressor arrival time windows to statically determine the effective loading seen by the victim.
It is yet a further object to initiate the process with a pessimistic solution to be successively refined to increase the accuracy of the result. Because the initial solution bounds the actual result, the results after any number of refinement iterations (e.g., before the method has converged) can be extracted and still ensure that the result bounds the actual circuit timing.
Briefly and in general terms, the present invention provides a method for factoring in coupling effects caused by interconnection wires while performing a static timing analysis on an integrated circuit chip, module, card, and the like, being designed. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on an overlap between an arrival time window of the selected nets and possible arrival time windows of nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.
In another embodiment of the present invention the updating the net capacitance of selected nets is based instead on the slew of selected nets and the slew of other nets which are coupled to the selected nets.
In yet another embodiment of the invention, updating of the net capacitance is based in a combination of both the overlap between the arrival time window of selected nets and the possible arrival time windows of nets which are coupled to the selected nets as well as the slew of selected nets and the slew of other nets which are coupled to the selected nets.